MC705P6ACDWE Freescale Semiconductor, MC705P6ACDWE Datasheet - Page 47

IC MCU 176 BYTES RAM 28-SOIC

MC705P6ACDWE

Manufacturer Part Number
MC705P6ACDWE
Description
IC MCU 176 BYTES RAM 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC705P6ACDWE

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SIO
Peripherals
POR, WDT
Number Of I /o
21
Program Memory Size
4.5KB (4.5K x 8)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC705P
Core
HC05
Data Bus Width
8 bit
Data Ram Size
176 B
Maximum Clock Frequency
2.1 MHz
Number Of Programmable I/os
21
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
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8.3.1 Timer Control Register
The timer control register (TCR), shown in
ICIE — Input Capture Interrupt Enable
OCIE — Output Compare Interrupt Enable
TOIE — Timer Overflow Interrupt Enable
IEDG — Input Edge
OLVL — Output Level
Freescale Semiconductor
This read/write bit enables interrupts caused by an active signal on the TCAP pin. Resets clear the
ICIE bit.
This read/write bit enables interrupts caused by an active signal on the TCMP pin. Resets clear the
OCIE bit.
This read/write bit enables interrupts caused by a timer overflow. Reset clear the TOIE bit.
The state of this read/write bit determines whether a positive or negative transition on the TCAP pin
triggers a transfer of the contents of the timer register to the input capture register. Resets have no
effect on the IEDG bit.
The state of this read/write bit determines whether a logic 1 or logic 0 appears on the TCMP pin when
a successful output compare occurs. Resets clear the OLVL bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
1 = Positive edge (low to high transition) triggers input capture
0 = Negative edge (high to low transition) triggers input capture
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
Enables input capture interrupts
Enables output compare interrupts
Enables timer overflow interrupts
Controls the active edge polarity of the TCAP signal
Controls the active level of the TCMP output
Address:
Reset:
Read:
Write:
$0012
Bit 7
ICIE
0
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Figure 8-2. Timer Control Register (TCR)
= Unimplemented
OCIE
6
0
TOIE
Figure
5
0
U = Undetermined
8-2, performs these functions:
4
0
0
3
0
0
2
0
0
IEDG
U
1
OLVL
Bit 0
Timer I/O Registers
0
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