MC705P6ACDWE Freescale Semiconductor, MC705P6ACDWE Datasheet - Page 48

IC MCU 176 BYTES RAM 28-SOIC

MC705P6ACDWE

Manufacturer Part Number
MC705P6ACDWE
Description
IC MCU 176 BYTES RAM 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC705P6ACDWE

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SIO
Peripherals
POR, WDT
Number Of I /o
21
Program Memory Size
4.5KB (4.5K x 8)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC705P
Core
HC05
Data Bus Width
8 bit
Data Ram Size
176 B
Maximum Clock Frequency
2.1 MHz
Number Of Programmable I/os
21
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Capture/Compare Timer
8.3.2 Timer Status Register
The timer status register (TSR), shown in
ICF — Input Capture Flag
OCF — Output Compare Flag
TOF — Timer Overflow Flag
48
The ICF bit is set automatically when an edge of the selected polarity occurs on the TCAP pin. Clear
the ICF bit by reading the timer status register with ICF set and then reading the low byte ($0015) of
the input capture registers. Resets have no effect on ICF.
The OCF bit is set automatically when the value of the timer registers matches the contents of the
output compare registers. Clear the OCF bit by reading the timer status register with OCF set and then
reading the low byte ($0017) of the output compare registers. Resets have no effect on OCF.
The TOF bit is set automatically when the 16-bit counter rolls over from $FFFF to $0000. Clear the
TOF bit by reading the timer status register with TOF set, and then reading the low byte ($0019) of the
timer registers. Resets have no effect on TOF.
An active signal on the TCAP pin, transferring the contents of the timer registers to the input
capture registers
A match between the 16-bit counter and the output compare registers, transferring the OLVL bit to
the TCMP pin
A timer roll over from $FFFF to $0000
Address:
Reset:
Read:
Write:
$0013
Bit 7
ICF
U
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Figure 8-3. Timer Status Register (TSR)
= Unimplemented
OCF
U
6
TOF
Figure
U
5
8-3, contains flags to signal the following conditions:
U = Undetermined
4
0
0
3
0
0
2
0
0
1
0
0
Freescale Semiconductor
Bit 0
0
0