MC705P6ACDWE Freescale Semiconductor, MC705P6ACDWE Datasheet - Page 51
Manufacturer Part Number
IC MCU 176 BYTES RAM 28-SOIC
Specifications of MC705P6ACDWE
Number Of I /o
Program Memory Size
4.5KB (4.5K x 8)
Program Memory Type
176 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Data Bus Width
Data Ram Size
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / Rohs Status
To prevent OCF from being set between the time it is read and the time the output compare registers are
updated, use this procedure:
8.4 Timer During Wait/Halt Mode
The CPU clock halts during the wait (or halt) mode, but the timer remains active. If interrupts are enabled,
a timer interrupt will cause the processor to exit the wait mode.
8.5 Timer During Stop Mode
In the stop mode, the timer stops counting and holds the last count value if STOP is exited by an interrupt.
If STOP is exited by RESET, the counters are forced to $FFFC. During STOP, if at least one valid input
capture edge occurs at the TCAP pins, the input capture detect circuit is armed. This does not set any
timer flags or wake up the MCU, but if an interrupt is used to exit stop mode, there is an active input
capture flag and data from the first valid edge that occurred during the stop mode. If reset is used to exit
stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred.
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code register.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Timer During Wait/Halt Mode