MC705P6ACDWE Freescale Semiconductor, MC705P6ACDWE Datasheet - Page 58

IC MCU 176 BYTES RAM 28-SOIC

MC705P6ACDWE

Manufacturer Part Number
MC705P6ACDWE
Description
IC MCU 176 BYTES RAM 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC705P6ACDWE

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SIO
Peripherals
POR, WDT
Number Of I /o
21
Program Memory Size
4.5KB (4.5K x 8)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC705P
Core
HC05
Data Bus Width
8 bit
Data Ram Size
176 B
Maximum Clock Frequency
2.1 MHz
Number Of Programmable I/os
21
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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EPROM
EPGM — EPROM Program Control
ELAT— EPROM Latch Control
To program a byte of EPROM, manipulate the EPROG register as follows:
This sequence is also shown in the sample program listing in
58
1. Set the ELAT bit in the EPROG register.
2. Write the desired data to the desired EPROM address.
3. Set the EPGM bit in the EPROG register for the specified programming time, t
4. Clear the ELAT and EPGM bits in the EPROG register.
If the EPGM bit is set, programming power is applied to the EPROM array. If the EPGM bit is cleared,
programming power is removed from the EPROM array. The EPGM bit cannot be set unless the ELAT
bit is set already.
Whenever the ELAT bit is cleared, the EPGM bit is cleared also. Both the EPGM and the ELAT bit
cannot be set using the same write instruction. Any attempt to set both the EPGM and ELAT bit on the
same write instruction cycle will result in the ELAT bit being set and the EPGM bit being cleared. The
EPGM bit is a read-write bit and can be read at any time. The EPGM bit is cleared by reset.
If the ELAT bit is set, the EPROM address and data bus are configured for programming to the array.
If the ELAT bit is cleared, the EPROM address and data bus are configured for normal reading of data
from the array. When the ELAT bit is set, the address and data bus are latched in the EPROM array
when a subsequent write to the array is made. Data in the EPROM array cannot be read if the ELAT
bit is set.
Whenever the ELAT bit is cleared, the EPGM bit is cleared also. Both the EPGM and the ELAT bit
cannot be set using the same write instruction. Any attempt to set both the EPGM and ELAT bit on the
same write instruction cycle will result in the ELAT bit being set and the EPGM bit being cleared. The
ELAT bit is a read-write bit and can be read at any time. The ELAT bit is cleared by reset.
00DB
00DD
00DF
001C
00D0
00D0
00D2
00D4
00D6
00D9
0055
0700
0000
Address $001C
Reset:
Read:
Write:
C7 07 00
B7 1C
AD 03
10 1C
3F 1C
Figure 10-1. EPROM Programming Register (EPROG)
A6 02
A6 55
Bit 7
81
0
0
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Table 10-1. EPROM Programming Routine
= Unimplemented
EPROM
EPROG
EPGM
6
0
0
DATA
ORG
BSET EPGM, EPROG
5
0
0
CLR EPROG
STA EPROG
STA EPROM
BSR DELAY
LDA #DATA
EQU $700
LDA #$04
EQU $1C
EQU $55
EQU $00
RTS
$D0
4
0
0
3
0
0
Table
EPGM BIT IN EPROG REG
WRITE IT TO EPROM LOC
TURN ON PGM VOLTAGE
CLR LAT AND PGM BITS
A SAMPLE EPROM ADX
SET LAT BIT IN EPROG
PROGRAMMING REG
WAIT 4 ms MINIMUM
ELAT
10-1.
2
0
DATA VALUE
DATA BYTE
1
0
0
Freescale Semiconductor
EPGM
EPGM
Bit 0
0
.