MC705P6ACDWE Freescale Semiconductor, MC705P6ACDWE Datasheet - Page 68

IC MCU 176 BYTES RAM 28-SOIC

MC705P6ACDWE

Manufacturer Part Number
MC705P6ACDWE
Description
IC MCU 176 BYTES RAM 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC705P6ACDWE

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SIO
Peripherals
POR, WDT
Number Of I /o
21
Program Memory Size
4.5KB (4.5K x 8)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC705P
Core
HC05
Data Bus Width
8 bit
Data Ram Size
176 B
Maximum Clock Frequency
2.1 MHz
Number Of Programmable I/os
21
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
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Central Processor Unit (CPU) Core
12.2.2 Index Register
The index register shown in
In indexed addressing with no offset, the index register contains the low byte of the operand address, and
the high byte is assumed to be $00. In indexed addressing with an 8-bit offset, the CPU finds the operand
address by adding the index register contents to an 8-bit immediate value. In indexed addressing with a
16-bit offset, the CPU finds the operand address by adding the index register contents to a 16-bit
immediate value.
The index register can also serve as an auxiliary accumulator for temporary storage. The index register
is unaffected by a reset of the device.
12.2.3 Stack Pointer
The stack pointer shown in
than 64 Kbytes, the unimplemented upper address lines are ignored. The stack pointer contains the
address of the next free location on the stack. During a reset or the reset stack pointer (RSP) instruction,
the stack pointer is set to $00FF. The stack pointer is then decremented as data is pushed onto the stack
and incremented as data is pulled from the stack.
When accessing memory, the 10 most significant bits are permanently set to 0000000011. The six least
significant register bits are appended to these 10 fixed bits to produce an address within the range of
$00FF to $00C0. Subroutines and interrupts may use up to 64 ($40) locations. If 64 locations are
exceeded, the stack pointer wraps around and writes over the previously stored information. A subroutine
call occupies two locations on the stack and an interrupt uses five locations.
12.2.4 Program Counter
The program counter shown in
less than 64 Kbytes, the unimplemented upper address lines are ignored. The program counter contains
the address of the next instruction or operand to be fetched.
Normally, the address in the program counter increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
12.2.5 Condition Code Register
The CCR shown in
instruction just executed. The fifth bit is the interrupt mask. These bits can be individually tested by a
program, and specific actions can be taken as a result of their state. The condition code register should
be thought of as having three additional upper bits that are always ones. Only the interrupt mask is
affected by a reset of the device. The following paragraphs explain the functions of the lower five bits of
the condition code register.
H — Half Carry Bit
68
When the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator
during the last ADD or ADC (add with carry) operation. The half-carry bit is required for binary-coded
decimal (BCD) arithmetic operations.
Indexed addressing
Temporary storage
Figure 12-1
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Figure 12-1
Figure 12-1
Figure 12-1
is a 5-bit register in which four bits are used to indicate the results of the
is a 16-bit register internally. In devices with memory maps less
is an 8-bit register that can perform two functions:
is a 16-bit register internally. In devices with memory maps
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