MC705P6ACDWE Freescale Semiconductor, MC705P6ACDWE Datasheet - Page 72

IC MCU 176 BYTES RAM 28-SOIC

MC705P6ACDWE

Manufacturer Part Number
MC705P6ACDWE
Description
IC MCU 176 BYTES RAM 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC705P6ACDWE

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SIO
Peripherals
POR, WDT
Number Of I /o
21
Program Memory Size
4.5KB (4.5K x 8)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC705P
Core
HC05
Data Bus Width
8 bit
Data Ram Size
176 B
Maximum Clock Frequency
2.1 MHz
Number Of Programmable I/os
21
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Instruction Set
13.2.4 Extended
Extended instructions use three bytes and can access any address in memory. The first byte is the
opcode; the second and third bytes are the high and low bytes of the operand address.
When using the Freescale assembler, the programmer does not need to specify whether an instruction is
direct or extended. The assembler automatically selects the shortest form of the instruction.
13.2.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses
within the first 256 memory locations. The index register contains the low byte of the effective address of
the operand. The CPU automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of
a frequently used RAM or I/O location.
13.2.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses
within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the
unsigned byte following the opcode. The sum is the effective address of the operand. These instructions
can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table
can begin anywhere within the first 256 memory locations and could extend as far as location 510
($01FE). The k value is typically in the index register, and the address of the beginning of the table is in
the byte following the opcode.
13.2.7 Indexed,16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at
any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand. The first byte after the opcode is
the high byte of the 16-bit offset; the second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere
in memory.
As with direct and extended addressing, the Freescale assembler determines the shortest form of
indexed addressing.
13.2.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the
effective branch destination by adding the signed byte following the opcode to the contents of the program
counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed,
two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Freescale assembler, the programmer does not need to calculate the offset, because the
assembler determines the proper offset and verifies that it is within the span of the branch.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
72
Freescale Semiconductor