R5F21265SDFP#U0 Renesas Electronics America, R5F21265SDFP#U0 Datasheet - Page 350
R5F21265SDFP#U0
Manufacturer Part Number
R5F21265SDFP#U0
Description
IC R8C/26 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/26r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21265SDFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21265SDFP#U0R5F21265SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 17.8
Timer RA Set the pulse width measurement level low
Timer RA Set the count source (f1, f2, f8, fOCO)
Timer RA Set the Synch Break width
Hardware LIN Set the LIN operation to stop
Hardware LIN Set to slave mode
Hardware LIN Set the LIN operation to start
Hardware LIN Set the RXD0 input unmasking timing
Hardware LIN Set the register to enable interrupts
Timer RA Set to pulse width measurement mode
Timer RA Set the INT1/TRAIO pin to P1_5
Sep 26, 2008
Bits TCK0 to TCK2 in the TRAMR register
TRAPRE register
TRA register
TEDGSEL bit in the TRAIOC register ← 0
Bits TMOD0 to TMOD2 in the TRAMR register ← 011b
TIOSEL bit in the TRAIOC register ← 1
LINE bit in the LINCR register ← 1
Example of Header Field Reception Flowchart (1)
(After Synch Break detection, or after Synch
Field measurement)
SBE bit in the LINCR register
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in the LINCR register
MST bit in the LINCR register ← 0
LINE bit in the LINCR register ← 0
Page 331 of 453
A
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
Set the count source and registers
TRA and TRAPRE as appropriate
for the Synch Break period.
Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after detection of Synch
Break, the Synch Field signal is
also input to UART0.
17. Hardware LIN
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