M30622F8PGP#U3C Renesas Electronics America, M30622F8PGP#U3C Datasheet - Page 278
M30622F8PGP#U3C
Manufacturer Part Number
M30622F8PGP#U3C
Description
IC M16C MCU FLASH 64K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30622F8PGP#U3C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Family Name
M16C
Maximum Speed
24 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
87
Interface Type
UART
On-chip Adc
26-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
11
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30622F8PGP#U3CM30622F8PGP#D3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30622F8PGP#U3CM30622F8PGP#D5C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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5.6 Multiple Interrupts
Chapter 5
The following shows the internal bit states when control has branched to an interrupt routine:
By setting the interrupt enable flag (I flag) (= 1) in the interrupt routine, you can reenable interrupts so that an
interrupt request can be acknowledged that has higher priority than the processor interrupt priority level
(IPL). Figure 5.6.1 shows how multiple interrupts are handled.
The interrupt requests that have not been acknowledged for their low interrupt priority level are kept pend-
ing. When the IPL is restored by an REIT instruction and interrupt priority is resolved against it, the pending
interrupt request is acknowledged if the following condition is met:
• The interrupt enable flag (I flag) is cleared to 0 (interrupts disabled).
• The interrupt request bit for the acknowledged interrupt is cleared to 0.
• The processor interrupt priority level (IPL) equals the interrupt priority level of the acknowledged interrupt.
pending interrupt request
Interrupt priority level of
Interrupt
>
260
Restored processor interrupt
priority level (IPL)
5.6 Multiple interrupts
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