DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 178
DF2398F20V
Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398F20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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When the RCW bit is set to 1, RAS signal output is delayed by one cycle. The width of the RAS signal should be adjusted
with bits RLW1 and RLW0. These bits are only enabled in refresh operations.
Figure 6-26 shows the timing when the RCW bit is set to 1.
Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this
mode, refresh timing and refresh addresses are generated within the DRAM.
To select self-refreshing, set the RFSHE bit and RMODE bit in DRAMCR to 1. Then, when a SLEEP instruction is
executed to enter software standby mode, the CAS and RAS signals are output and DRAM enters self-refresh mode, as
shown in figure 6-27.
When software standby mode is exited, the RMODE bit is cleared to 0 and self-refresh mode is cleared.
When switching to software standby mode, if there is a CBR refresh request, CBR refreshing is executed before self-
refresh mode is entered.
Rev.6.00 Oct.28.2004 page 148 of 1016
REJ09B0138-0600H
CSn, (RAS)
CAS, LCAS
Figure 6-26 CBR Refresh Timing (When RCW = 1, RLW1 = 0, RLW0 = 1)
CAS, LCAS
Note: n = 2 to 5
CS, (RAS)
ø
Note: n = 2 to 5
ø
T
Rp
Figure 6-25 CBR Refresh Timing
T
Rp
T
Rr
T
Rr
T
Rc1
T
Rc1
T
Rw
T
Rc2
T
Rc2
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