DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 242
DF2398F20V
Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398F20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
Company:
Part Number:
DF2398F20V
Manufacturer:
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Quantity:
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DF2398F20V
Manufacturer:
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Figure 7-14 illustrates operation in block transfer mode when MARA is designated as a block area.
ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request,
burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH.
At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA
is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit is cleared and transfer
ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to the CPU or DTC.
Figure 7-15 shows the operation flow in block transfer mode.
Rev.6.00 Oct.28.2004 page 212 of 1016
REJ09B0138-0600H
Address T
Address B
Legend:
Address
Address
Address
Address
Where :
A
A
T
T
B
B
L
L
N
M
A
B
A
B
A
B
= L
= L
= L
= L
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
Figure 7-14 Operation in Block Transfer Mode (BLKDIR = 1)
A
B
A
B
+ SAIDE · (–1)
+ DAIDE · (–1)
Block area
SAID
DAID
· (2
· (2
DTSZ
DTSZ
Consecutive transfer
of M bytes or words
is performed in
response to one
request
· (N–1))
· (M·N–1))
Transfer
2nd block
1st block
Nth block
Address T
Address B
B
B
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