DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 277
DF2398F20V
Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398F20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It
functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer
ends when the count reaches H'0000.
8.2.7
The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF, with bits corresponding to
the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt
sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources
and DTCE bits is shown in table 8-4, together with the vector number generated for each interrupt controller.
For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions such as BSET and
BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable
interrupts and write after executing a dummy read on the relevant register.
8.2.8
Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read.
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector
number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
Bit
Initial value :
R/W
Bit
Initial value :
R/W
DTC Enable Registers (DTCER)
DTC Vector Register (DTVECR)
Bit n
DTCEn
0
1
:
:
:
:
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
DTCE7
R/(W)*
R/W
7
0
7
0
Description
DTC activation by this interrupt is disabled
[Clearing conditions]
DTC activation by this interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
When the DISEL bit is 1 and the data transfer has ended
When the specified number of transfers have ended
DTCE6
R/W
R/W
6
0
6
0
DTCE5
R/W
R/W
5
0
5
0
DTCE4
R/W
R/W
4
0
4
0
DTCE3
R/W
R/W
3
0
3
0
DTCE2
R/W
R/W
2
0
2
0
DTCE1
R/W
R/W
Rev.6.00 Oct.28.2004 page 247 of 1016
1
0
1
0
DTCE0
R/W
R/W
0
0
0
0
(Initial value)
REJ09B0138-0600H
(n = 7 to 0)
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