DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 502
DF2398F20V
Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398F20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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For details of the multiprocessor communication function, see section 14.3.3, Multiprocessor Communication Function.
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The
clock source can be selected from ø, ø/4, ø/16, and ø/64, according to the setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see section 14.2.8, Bit Rate
Register (BRR).
14.2.6
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode,
and interrupt requests, and selection of the serial clock source.
SCR can be read or written to by the CPU at all times.
SCR is initialized to H'00 by a reset, and by putting the device in standby mode or module stop mode. In the H8S/2398,
H8S/2394, H8S/2392, and H8S/2390, however, the value in SCR is initialized to H'00 by a reset, or in hardware standby
mode, but SCR retains its current state when the device enters software standby mode or module stop mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt (TXI) request generation
when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1.
Note:* TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or
Rev.6.00 Oct.28.2004 page 472 of 1016
REJ09B0138-0600H
Bit
Initial value :
R/W
clearing the TIE bit to 0.
Serial Control Register (SCR)
Bit 2
MP
0
1
Bit 1
CKS1
0
1
Bit 7
TIE
0
1
:
:
R/W
TIE
7
0
Description
Multiprocessor function disabled
Multiprocessor format selected
Bit 0
CKS0
0
1
0
1
Description
Transmit data empty interrupt (TXI) requests disabled*
Transmit data empty interrupt (TXI) requests enabled
R/W
RIE
6
0
Description
ø clock
ø/4 clock
ø/16 clock
ø/64 clock
R/W
TE
5
0
R/W
RE
4
0
MPIE
R/W
3
0
TEIE
R/W
2
0
CKE1
R/W
1
0
CKE0
R/W
0
0
(Initial value)
(Initial value)
(Initial value)
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