DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 556
DF2398F20V
Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398F20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
DF2398F20V
Manufacturer:
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Quantity:
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Manufacturer:
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15.3.4
Table 15-3 shows a bit map of the registers used by the Smart Card interface.
Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below.
Table 15-3 Smart Card Interface Register Settings
Notes: — : Not used.
SMR Setting: The GM bit is cleared to 0 in normal Smart Card interface mode, and set to 1 in GSM mode. The O/E bit is
cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 15.3.5, Clock.
BRR Setting: BRR is used to set the bit rate. See section 15.3.5, Clock, for the method of calculating the value to be set.
SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 14,
Serial Communication Interface (SCI).
Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock
is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed.
The clock output can also be fixed high or low.
Smart Card Mode Register (SCMR) Setting:
The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type.
The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type.
The SMIF bit is set to 1 in the case of the Smart Card interface.
Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct
convention and inverse convention).
Rev.6.00 Oct.28.2004 page 526 of 1016
REJ09B0138-0600H
* The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0.
Register Settings
Register
SMR
BRR
SCR
TDR
SSR
RDR
SCMR
Bit 7
GM
BRR7
TIE
TDR7
TDRE
RDR7
—
Bit 6
0
BRR6
RIE
TDR6
RDRF
RDR6
—
Bit 5
1
BRR5
TE
TDR5
ORER
RDR5
—
Bit 4
O/E
BRR4
RE
TDR4
ERS
RDR4
—
Bit
Bit 3
1
BRR3
0
TDR3
PER
RDR3
SDIR
Bit 2
0
BRR2
0
TDR2
TEND
RDR2
SINV
Bit 1
CKS1
BRR1
CKE1*
TDR1
0
RDR1
—
Bit 0
CKS0
BRR0
CKE0
TDR0
0
RDR0
SMIF
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