DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 576
DF2398F20V
Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398F20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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16.3
ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the
bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP).
A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the
CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are
transferred to the CPU.
When reading ADDR. always read the upper byte before the lower byte. It is possible to read only the upper byte, but if
only the lower byte is read, incorrect data may be obtained.
Figure 16-2 shows the data flow for ADDR access.
16.4
The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode
and scan mode.
16.4.1
Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when
the ADST bit is set to 1, according to the software or external trigger input. The ADST bit remains set to 1 during A/D
conversion, and is automatically cleared to 0 when conversion ends.
Rev.6.00 Oct.28.2004 page 546 of 1016
REJ09B0138-0600H
Interface to Bus Master
Operation
Single Mode (SCAN = 0)
Bus master
(H'AA)
Bus master
(H'40)
Lower byte read
Upper byte read
Figure 16-2 ADDR Access Operation (Reading H'AA40)
Bus interface
Bus interface
ADDRnH
ADDRnH
(H'AA)
(H'AA)
ADDRnL
ADDRnL
(H'40)
(H'40)
TEMP
TEMP
Module data bus
(H'40)
Module data bus
(H'40)
(n = A to D)
(n = A to D)
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