HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 222
HD64F7047F50V
Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Specifications of HD64F7047F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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10.3.4
The TIER registers are 8-bit readable/writable registers that control enabling or disabling of
interrupt requests for each channel. The MTU has five TIER registers, one for each channel.
Rev. 2.00, 09/04, page 180 of 720
Bit
7
6
5
4
3
Bit Name
TTGE
TCIEU
TCIEV
TGIED
Timer Interrupt Enable Register (TIER)
Initial
value
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R
A/D Conversion Start Request Enable
TGR Interrupt Enable D
Description
Enables or disables generation of A/D conversion start
requests by TGRA input capture/compare match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
Reserved
This bit is always read as 1, and should only be written with
1.
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the TCFU
flag when the TCFU flag in TSR is set to 1 in channels 1
and 2.
In channels 0, 3, and 4, bit 5 is reserved. It is always read
as 0, and should only be written with 0.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the TCFV
flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
Enables or disables interrupt requests (TGID) by the TGFD
bit when the TGFD bit in TSR is set to 1 in channels 0, 3,
and 4.
In channels 1 and 2, bit 3 is reserved. It is always read as 0,
and should only be written with 0.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
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