HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 636
HD64F7047F50V
Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Specifications of HD64F7047F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Price
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Quantity:
30 000
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Part Number:
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Quantity:
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Part Number:
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Manufacturer:
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Quantity:
20 000
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23.1.2
Figure 23.1 shows a block diagram of the AUD.
23.2
Table 23.1 shows the AUD's input/output pins.
Table 23.1 AUD Pins
Rev. 2.00, 09/04, page 594 of 720
Name
AUD data
AUD reset
AUD mode
AUD clock
AUD sync signal
AUDATA0
AUDATA1
AUDATA2
AUDATA3
AUDRST
AUDMD
AUDCK
AUDSYNC
Block Diagram
Pin Configuration
AUDATA3 to
AUDATA0
AUDRST
AUDMD
AUDCK
AUDSYNC
Abbreviation
PC output circuit
Address buffer
Mode control
Data buffer
Figure 23.1 AUD Block Diagram
Branch Trace Mode
Branch destination address
output
AUD reset input
Mode select input (L)
Sync clock (φ/2) output
Data start position
identification signal output
controller
Bus
CPU
Internal
bus
Function
RAM Monitor Mode
Monitor address/data
input/output
AUD reset input
Mode select input (H)
Sync clock input
Data start position
identification signal input
Peripheral
module bus
peripheral
memory
On-chip
On-chip
module
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