MC68LK332ACAG16 Freescale Semiconductor, MC68LK332ACAG16 Datasheet - Page 51

IC MCU 32BIT LV AMASK 144-LQFP

MC68LK332ACAG16

Manufacturer Part Number
MC68LK332ACAG16
Description
IC MCU 32BIT LV AMASK 144-LQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68LK332ACAG16

Core Processor
CPU32
Core Size
32-Bit
Speed
16.78MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Interface Type
QSPI, SCI, UART
Minimum Operating Temperature
- 40 C
No. Of I/o's
15
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
16
Embedded Interface Type
QSPI, SCI, UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Data Ram Size
2 KB
Number Of Programmable I/os
15
Number Of Timers
16
Cpu Family
68K/M683xx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Program Memory Size
Not Required
Total Internal Ram Size
2KB
# I/os (max)
15
Number Of Timers - General Purpose
16
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC68LK332ACAG16
Manufacturer:
MOTOLOLA
Quantity:
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Part Number:
MC68LK332ACAG16
Manufacturer:
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Quantity:
10 000
4.7 Background Debugging Mode
MC68332
MC68332TS/D
The background debugger on the CPU32 is implemented in CPU microcode. The background debug-
ging commands are summarized below.
Read Memory Location
Write Memory Location
Read System Register
Write System Register
Dump Memory Block
Resume Execution
Read D/A Register
Write D/A Register
Reset Peripherals
Fill Memory Block
Patch User Code
No Operation
Command
Freescale Semiconductor, Inc.
WDREG/WAREG The data operand is written to the specified address or data
RDREG/RAREG
For More Information On This Product,
Mnemonic
Table 21 Background Debuggung Mode
WSREG
RSREG
WRITE
DUMP
READ
CALL
NOP
FILL
RST
GO
Go to: www.freescale.com
Read the selected address or data register and return the
results through the serial interface.
register.
The specified system control register is read. All registers that
can be read in supervisor mode can be read in background
mode.
The operand data is written into the specified system control
register.
Read the sized data at the memory location specified by the
long-word address. The source function code register (SFC)
determines the address space accessed.
Write the operand data to the memory location specified by the
long-word address. The destination function code (DFC)
register determines the address space accessed.
Used in conjunction with the READ command to dump large
blocks of memory. An initial READ is executed to set up the
starting address of the block and retrieve the first result.
Subsequent operands are retrieved with the DUMP command.
Used in conjunction with the WRITE command to fill large
blocks of memory. Initially, a WRITE is executed to set up the
starting address of the block and supply the first operand. The
FILL command writes subsequent operands.
The pipe is flushed and refilled before resuming instruction
execution at the current PC.
Current program counter is stacked at the location of the
current stack pointer. Instruction execution begins at user
patch code.
Asserts RESET for 512 clock cycles. The CPU is not reset by
this command. Synonymous with the CPU RESET instruction.
NOP performs no operation and can be used as a null
command.
Description
MOTOROLA
51