MC68LK332ACAG16 Freescale Semiconductor, MC68LK332ACAG16 Datasheet - Page 53

IC MCU 32BIT LV AMASK 144-LQFP

MC68LK332ACAG16

Manufacturer Part Number
MC68LK332ACAG16
Description
IC MCU 32BIT LV AMASK 144-LQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68LK332ACAG16

Core Processor
CPU32
Core Size
32-Bit
Speed
16.78MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Interface Type
QSPI, SCI, UART
Minimum Operating Temperature
- 40 C
No. Of I/o's
15
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
16
Embedded Interface Type
QSPI, SCI, UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Data Ram Size
2 KB
Number Of Programmable I/os
15
Number Of Timers
16
Cpu Family
68K/M683xx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Program Memory Size
Not Required
Total Internal Ram Size
2KB
# I/os (max)
15
Number Of Timers - General Purpose
16
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC68LK332ACAG16
Manufacturer:
MOTOLOLA
Quantity:
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Part Number:
MC68LK332ACAG16
Manufacturer:
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Quantity:
10 000
5.1.2 Input Capture/Input Transition Counter (ITC)
5.1.3 Output Compare (OC)
5.1.4 Pulse-Width Modulation (PWM)
5.1.5 Synchronized Pulse-Width Modulation (SPWM)
5.1.6 Period Measurement with Additional Transition Detect (PMA)
MC68332
MC68332TS/D
one of three ways:
Any channel of the TPU can capture the value of a specified TCR upon the occurrence of each transition
or specified number of transitions, and then generate an interrupt request to notify the CPU. A channel
can perform input captures continually, or a channel can detect a single transition or specified number
of transitions, then cease channel activity until reinitialization. After each transition or specified number
of transitions, the channel can generate a link to a sequential block of up to eight channels. The user
specifies a starting channel of the block and the number of channels within the block. The generation
of links depends on the mode of operation. In addition, after each transition or specified number of tran-
sitions, one byte of the parameter RAM (at an address specified by channel parameter) can be incre-
mented and used as a flag to notify another channel of a transition.
The output compare function generates a rising edge, falling edge, or a toggle of the previous edge in
This algorithm generates a 50% duty-cycle continuous square wave with each high/low time equal to
the calculated OFFSET. Due to offset calculation, there is an initial link time before continuous pulse
generation begins.
The TPU can generate a pulse-width modulation waveform with any duty cycle from zero to 100% (with-
in the resolution and latency capability of the TPU). To define the PWM, the CPU provides one param-
eter that indicates the period and another parameter that indicates the high time. Updates to one or both
of these parameters can direct the waveform change to take effect immediately, or coherently beginning
at the next low-to-high transition of the pin.
The TPU generates a PWM waveform in which the CPU can change the period and/or high time at any
time. When synchronized to a time function on a second channel, the synchronized PWM low-to-high
transitions have a time relationship to transitions on the second channel.
This function and the following function are used primarily in toothed-wheel speed-sensing applications,
such as monitoring rotational speed of an engine. The period measurement with additional transition
detect function allows for a special-purpose 23-bit period measurement. It can detect the occurrence of
an additional transition (caused by an extra tooth on the sensed wheel) indicated by a period measure-
ment that is less than a programmable ratio of the previous period measurement.
Once detected, this condition can be counted and compared to a programmable number of additional
transitions detected before TCR2 is reset to $FFFF. Alternatively, a byte at an address specified by a
channel parameter can be read and used as a flag. A nonzero value of the flag indicates that TCR2 is
to be reset to $FFFF once the next additional transition is detected.
1. Immediately upon CPU initiation, thereby generating a pulse with a length equal to a program-
2. At a programmable delay time from a user-specified time.
3. Continuously. Upon receiving a link from a channel, OC references, without CPU interaction, a
mable delay time.
specifiable period and calculates an offset:
where Ratio is a parameter supplied by the user.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Offset = Period Ratio
MOTOROLA
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