DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1294
DF70845AD80FPV
Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet
1.DF70844AD80FPV.pdf
(1644 pages)
Specifications of DF70845AD80FPV
Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 23 Flash Memory
Table 23.6 Usable Parameters and Target Modes
Note:
(1) Download Control
Rev. 3.00 May 17, 2007 Page 1236 of 1582
REJ09B0181-0300
Name of
Parameter
Download pass/fail
result
Flash pass/fail
result
Flash
programming/
erasing frequency
control
Flash user branch
address set
Flash multipurpose
address area
Flash multipurpose
data destination
area
Flash erase block
select
The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip
RAM area to be downloaded is the area as much as 3 kbytes starting from the start address
specified by FTDAR. For the address map of the on-chip RAM, see figure 23.10.
The download control is set by using the programming/erasing interface registers. The return
value is given by the DPFR parameter.
(a) Download pass/fail result parameter (DPFR: one byte of start address of on-chip RAM
specified by FTDAR)
This parameter indicates the return value of the download result. The value of this
parameter can be used to determine if downloading is executed or not. Since the
confirmation whether the SCO bit is set to 1 is difficult, the certain determination must be
performed by setting one byte of the start address of the on-chip RAM area specified by
FTDAR to a value other than the return value of download (for example, H'FF) before the
download start (before setting the SCO bit to 1). For the checking method of download
results, see section 23.5.2 (2), Programming Procedure in User Program Mode.
*
One byte of start address of download destination specified by FTDAR
Abbrevia-
tion
DPFR
FPFR
FPEFEQ
FUBRA
FMPAR
FMPDR
FEBS
Down-
load
√
—
—
—
—
—
—
Initiali-
zation
—
√
√
√
—
—
—
Pro-
gram-
ming Erasure R/W
—
√
—
—
√
√
—
—
√
—
—
—
—
√
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial
Value
Undefined On-chip
Undefined R0 of CPU
Undefined R4 of CPU
Undefined R5 of CPU
Undefined R5 of CPU
Undefined R4 of CPU
Undefined R4 of CPU
Allocation
RAM*
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