DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 308
DF70845AD80FPV
Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet
1.DF70844AD80FPV.pdf
(1644 pages)
Specifications of DF70845AD80FPV
Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 308 of 1644
- Download datasheet (10Mb)
Section 9 Bus State Controller (BSC)
Rev. 3.00 May 17, 2007 Page 250 of 1582
REJ09B0181-0300
Bit
18 to 16
15 to 13
12, 11
Bit Name
WW[2:0]
SW[1:0]
Initial
Value
000
All 0
00
R/W
R/W
R
R/W
Description
Number of Wait Cycles in Write Access
Specify the number of cycles required for write access.
000: The same cycles as WR3 to WR0 settings (read
001: 0 cycles
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from Address and CSn
Assertion to RD and WRxx Assertion
Specify the number of delay cycles from address and
CSn assertion to RD and WRxx assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
access wait)
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