DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 32

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Figure 10.15 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 416
Figure 10.16 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 416
Figure 10.17 Example of DREQ Input Detection in Burst Mode Level Detection .................... 417
Figure 10.18 DMA Transfer End Timing (in Cycle Steal Level Detection)............................... 417
Figure 10.19 BSC Ordinary Memory Access
Figure 10.20 Example of Timing of DMAC Operation—Activation by DREQ
Figure 10.21 Example of DMAC Operation Timing— Activation by an On-Chip
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 11.1 Block Diagram of MTU2 ........................................................................................ 430
Figure 11.2 Complementary PWM Mode Output Level Example ............................................. 497
Figure 11.3 PWM Output Level Setting Procedure in Buffer Operation.................................... 502
Figure 11.4 Example of Counter Operation Setting Procedure .................................................. 515
Figure 11.5 Free-Running Counter Operation ............................................................................ 516
Figure 11.6 Periodic Counter Operation..................................................................................... 517
Figure 11.7 Example of Setting Procedure for Waveform Output by Compare Match.............. 517
Figure 11.8 Example of 0 Output/1 Output Operation ............................................................... 518
Figure 11.9 Example of Toggle Output Operation ..................................................................... 518
Figure 11.10 Example of Input Capture Operation Setting Procedure ....................................... 519
Figure 11.11 Example of Input Capture Operation .................................................................... 520
Figure 11.12 Example of Synchronous Operation Setting Procedure ........................................ 521
Figure 11.13 Example of Synchronous Operation...................................................................... 522
Figure 11.14 Compare Match Buffer Operation......................................................................... 523
Figure 11.15 Input Capture Buffer Operation............................................................................. 524
Figure 11.16 Example of Buffer Operation Setting Procedure................................................... 524
Figure 11.17 Example of Buffer Operation (1) .......................................................................... 525
Figure 11.18 Example of Buffer Operation (2) .......................................................................... 526
Figure 11.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for TGRC_0
Figure 11.20 Cascaded Operation Setting Procedure ................................................................. 528
Figure 11.21 Cascaded Operation Example (a) .......................................................................... 529
Figure 11.22 Cascaded Operation Example (b).......................................................................... 529
Figure 11.23 Cascaded Operation Example (c) .......................................................................... 530
Figure 11.24 Cascaded Operation Example (d).......................................................................... 531
Rev. 3.00 May 17, 2007 Page xxxii of Iviii
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device) ............................... 418
(in the Case of Cycle Stealing Transfer, Dual Address Mode,
Low-Level Detection, Iφ:Bφ:Pφ = 1:1/2:1/2, Data Transfer from External
Memory to External Memory, and Idle/Wait = 0)................................................. 419
Peripheral Module (in the Case of Cycle Stealing Transfer, Dual Address Mode,
Low-Level Detection, Iφ:Bφ:Pφ = 1:1/2:1/2, and Data Transfer from On-Chip
Peripheral Module to On-Chip RAM)................................................................... 420
to TGRA_0 Transfer Timing................................................................................. 527