DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 320
DF70845AD80FPV
Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet
1.DF70844AD80FPV.pdf
(1644 pages)
Specifications of DF70845AD80FPV
Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 320 of 1644
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Section 9 Bus State Controller (BSC)
Rev. 3.00 May 17, 2007 Page 262 of 1582
REJ09B0181-0300
Bit
8, 7
6, 5
4, 3
2
Bit Name
A3CL[1:0]
TRWL[1:0] 00
Initial
Value
10
All 0
0
R/W
R/W
R
R/W
R
Description
CAS Latency for Area 3
Specify the CAS latency for area 3.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Wait Cycles for Precharge Activation
Specify the minimum number of wait cycles to be
inserted for activation of precharge.
•
•
The setting for areas 2 and 3 is common.
00: 0 cycle (No wait cycles)
01: 1 cycle
10: 2 cycles
11: 3 cycles
Reserved
This bit is always read as 0. The write value should
always be 0.
From issuance of WRITA command by this LSI until
auto precharge is activated in SDRAM:
ACTV command is issued for the same bank in non-
bank active mode.
See the datasheet of the SDRAM to find the number
of cycles taken from the acceptance of WRITA
command by SDRAM until auto-precharge is
activated. These bits should be set so that the
above number of cycles will not exceed the number
of cycles specified by these bits.
From issuance of WRIT command by this LSI until
issuance of PRE command:
Different row addresses in the same bank are
accessed in bank active mode.
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