DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 60

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 1 Overview
Table 1.1
Rev. 3.00 May 17, 2007 Page 2 of 1582
REJ09B0181-0300
Items
CPU
Operating modes
User break controller
(UBC)
On-chip ROM
Features
Specification
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Note:
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Central processing unit with an internal 32-bit RISC (Reduced
Instruction Set Computer) architecture
Instruction length: 16-bit fixed length for improved code efficiency
Load-store architecture (basic operations are executed between
registers)
Sixteen 32-bit general registers
Five-stage pipeline
On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits)
executed in two to five cycles
C language-oriented 62 basic instructions
Operating modes
 Single chip mode
 Extended ROM enabled mode
 Extended ROM disabled mode
Operating states
 Program execution state
 Exception handling state
 Bus release state
Power-down modes
 Sleep mode
 Software standby mode
 Deep software standby mode
 Module standby mode
Addresses, data values, type of access, and data size can all be set as
break conditions
Supports a sequential break function
Two break channels
256 kbytes or 512 kbytes
Some specifications on slot illegal instruction exception handling
in this LSI differ from those of the conventional SH-2. For details,
see section 5.8.4, Notes on Slot Illegal Instruction Exception
Handling.