DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 700
DF70845AD80FPV
Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet
1.DF70844AD80FPV.pdf
(1644 pages)
Specifications of DF70845AD80FPV
Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Pin initialization procedures are described below for the numbered combinations in table 11.59.
The active level is assumed to be low.
Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted
in Normal Mode: Figure 11.137 shows an explanatory diagram of the case where an error occurs
in normal mode and operation is restarted in normal mode after re-setting.
MTU2 module output
1. After a reset, MTU2 output is low and ports are in the high-impedance state.
2. After a reset, the TMDR setting is for normal mode.
3. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR.
4. Initialize the pins with TIOR. (The example shows initial high output, with low output on
5. Set MTU2 output with the PFC.
6. The count operation is started by TSTR.
7. Output goes low on compare-match occurrence.
8. An error occurs.
9. Set port output with the PFC and output the inverse of the active level.
10. The count operation is stopped by TSTR.
11. Not necessary when restarting in normal mode.
12. Initialize the pins with TIOR.
13. Set MTU2 output with the PFC.
14. Operation is restarted by TSTR.
Rev. 3.00 May 17, 2007 Page 642 of 1582
REJ09B0181-0300
compare-match occurrence.)
Figure 11.137 Error Occurrence in Normal Mode, Recovery in Normal Mode
Port output
n = 0 to 15
TIOC*A
TIOC*B
PEn
PEn
RESET
1
(normal)
TMDR
2
High-Z
High-Z
TOER
(1)
3
0 out)
TIOR
(1 init
4
(MTU2)
PFC
5
TSTR
(1)
6
Match
7
occurs
Error
8
(PORT)
PFC
9
TSTR
10
(0)
(normal)
TMDR
11
0 out)
TIOR
(1 init
12
(MTU2)
PFC
13
TSTR
(1)
14
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