HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 351
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Bit
15
14
13
12
Bit Name
POE3F
POE2F
POE1F
POE0F
Initial
value
0
0
0
0
R/W
R/(W)* POE3 Flag
R/(W)* POE2 Flag
R/(W)* POE1 Flag
R/(W)* POE0 Flag
Description
This flag indicates that a high impedance request has been
input to the POE3 pin
[Clear condition]
•
[Set condition]
•
This flag indicates that a high impedance request has been
input to the POE2 pin
[Clear condition]
•
[Set condition]
•
This flag indicates that a high impedance request has been
input to the POE1 pin
[Clear condition]
•
[Set condition]
•
This flag indicates that a high impedance request has been
input to the POE0 pin
[Clear condition]
•
[Set condition]
•
By writing 0 to POE3F after reading a POE3F = 1
When the input set by ICSR1 bits 7 and 6 occurs at the
POE3 pin
By writing 0 to POE2F after reading a POE2F = 1
When the input set by ICSR1 bits 5 and 4 occurs at the
POE2 pin
By writing 0 to POE1F after reading a POE1F = 1
When the input set by ICSR1 bits 3 and 2 occurs at the
POE1 pin
By writing 0 to POE0F after reading a POE0F = 1
When the input set by ICSR1 bits 1 and 0 occurs at the
POE0 pin
Rev. 2.00, 09/04, page 309 of 720
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