HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 38
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Table 8.3
Table 8.4
Table 8.5
Table 8.6
Section 9 Bus State Controller (BSC)
Table 9.1
Table 9.2
Table 9.3
Section 10 Multi-Function Timer Pulse Unit (MTU)
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.7
Table 10.8
Table 10.9
Table 10.10
Table 10.11
Table 10.12
Table 10.13
Table 10.14
Table 10.15
Table 10.16
Table 10.17
Table 10.18
Table 10.19
Table 10.20
Table 10.21
Table 10.22
Table 10.23
Table 10.24
Table 10.25
Table 10.26
Table 10.27
Table 10.28
Table 10.29
Table 10.30
Table 10.31
Table 10.32
Table 10.33
Rev. 2.00, 09/04, page xxxvi of xl
Repeat Mode Register Functions .......................................................................... 124
Block Transfer Mode Register Functions ............................................................. 125
Execution State of DTC........................................................................................ 128
State Counts Needed for Execution State ............................................................. 128
Pin Configuration.................................................................................................. 135
Address Map......................................................................................................... 137
On-chip Peripheral I/O Register Access ............................................................... 148
MTU Functions..................................................................................................... 150
MTU Pins ............................................................................................................. 153
CCLR0 to CCLR2 (channels 0, 3, and 4) ............................................................. 157
CCLR0 to CCLR2 (channels 1 and 2) .................................................................. 157
TPSC0 to TPSC2 (channel 0) ............................................................................... 158
TPSC0 to TPSC2 (channel 1) ............................................................................... 158
TPSC0 to TPSC2 (channel 2) ............................................................................... 159
TPSC0 to TPSC2 (channels 3 and 4).................................................................... 159
MD0 to MD3 ........................................................................................................ 161
TIORH_0 (channel 0) ....................................................................................... 164
TIORH_0 (channel 0) ....................................................................................... 165
TIORL_0 (channel 0)........................................................................................ 166
TIORL_0 (channel 0)........................................................................................ 167
TIOR_1 (channel 1) .......................................................................................... 168
TIOR_1 (channel 1) .......................................................................................... 169
TIOR_2 (channel 2) .......................................................................................... 170
TIOR_2 (channel 2) .......................................................................................... 171
TIORH_3 (channel 3) ....................................................................................... 172
TIORH_3 (channel 3) ....................................................................................... 173
TIORL_3 (channel 3)........................................................................................ 174
TIORL_3 (channel 3)........................................................................................ 175
TIORH_4 (channel 4) ....................................................................................... 176
TIORH_4 (channel 4) ....................................................................................... 177
TIORL_4 (channel 4)........................................................................................ 178
TIORL_4 (channel 4)........................................................................................ 179
Output Level Select Function ........................................................................... 189
Output Level Select Function ........................................................................... 190
Output level Select Function............................................................................. 192
Register Combinations in Buffer Operation ..................................................... 202
Cascaded Combinations.................................................................................... 206
PWM Output Registers and Output Pins .......................................................... 208
Phase Counting Mode Clock Input Pins ........................................................... 212
Up/Down-Count Conditions in Phase Counting Mode 1.................................. 213
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