HD64F7047FW40V Renesas Electronics America, HD64F7047FW40V Datasheet - Page 627
HD64F7047FW40V
Manufacturer Part Number
HD64F7047FW40V
Description
MCU 5V 256K I-TEMP,PB-FREE 100-Q
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheet
1.HD64F7047F50V.pdf
(766 pages)
Specifications of HD64F7047FW40V
Core Processor
SH-2
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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22.3.2
The status register (SDSR) is a 16-bit register that can be read and written to by the CPU. The
SDSR value can be output from TDO, but serial data cannot be written to SDSR via TDI. The
SDTRF bit is output by means of a one-bit shift. In a two-bit shift, the SDTRF bit is output first,
followed by a reserved bit.
SDSR is initialized by TRST signal input, but is not initialized in software standby mode.
Bit
15 to
12
11
10 to 1
0
Bit Name
SDTRF
Status Register (SDSR)
Initial
Value
All 0
1
All 0
1
R/W
R
R
R
R/W
Description
Reserved
These bits are always read as 0, and should only be
written with 0.
Reserved
This bit is always read as 1, and should always be
written with 1.
Reserved
These bits are always read as 0, and should only be
written with 0.
Serial Data Transfer Control Flag
Indicates whether H-UDI registers can be accessed by
the CPU. The SDTRF bit is initialized by the TRST
signal, but is not initialized by a reset or in software
standby mode.
0: Serial transfer to SDDR has ended, and SDDR can
1: Serial transfer to SDDR is in progress.
be accessed.
Rev. 2.00, 09/04, page 585 of 720
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