M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 229

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
R
R
e
E
3
. v
J
2
Figure 17.10 Transmit and Receive Operation
0
C
1
9
8 /
0 .
B
(1) Transmit Timing (Internal clock selected)
Transfer Clock
TE bit in UiC1
register
TI bit in UiC1
register
CTSi
CLKi
TxDi
TXEPT bit in
UiC0 register
IR bit in SiTIC
register
0
1
The above applies to the following settings:
4
0
• The CKDIR bit in the UiMR register is set to "0" (internal clock selected)
• The CRD bit in the UiC
• The CKPOL bit the in UiC
• The UiIRS bit in the UiC
IR bit in SiRIC
register
OER bit in UiRB
register
RE bit in UiC1
register
CLKi
RxDi
TE bit in UiC1
register
TI bit in UiC1
register
RTSi
RI bit in UiC1
register
(2) Receive Timing (External clock selected)
G
The CRS bit is set to "0" (CTS function selected)
falling edge of the transfer clock)
f
3
The above applies to the following settings:
J
EXT
6
• The CKDIR bit in the UiMR register is set to "1" (external clock selected)
• The CRD bit in the UiC
• The CKPOL bit in the UiC0 register is set to "0"
u
o r
The CRS bit is set to "1" (RTS function selected)
(Data is received on the rising edge of the transfer clock)
0 -
. l
: External clock frequency
u
0
1
p
, 7
0
1
(
2
M
0
3
0
"H"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"L"
2
5
C
"H"
"1"
"0"
"1"
"0"
"1"
"0"
"L"
"1"
"0"
"1"
"0"
"1"
"0"
8 /
Page 206
0
, 4
1
Data is set in the UiTB register
register is set to "0" (RTS/CTS function enabled)
Date is transferred from the UARTi
receive register to the UiRB register
0
register is set to "0" (no data in the UiTB register)
0
register is set to "0" (data transmitted on the
M
register is set to "0" (RTS/CTS function enabled)
D
3
0
i=0 to 4
2
Data is transferred from the UiTB register to the UARTi transmit register
D
C
1
D
0
8 /
f o
T
D
CLK
2
D
4
1
4
D
) T
9
3
D
5
2
D
Dummy data is set in the UiTB register
Tc
4
D
3
D
5
D
4
1 / f
D
Received data is taken in
6
D
5
EXT
D
Set to "0" by an interrupt request acknowledgement or by program
7
D
Pulse stops because an "H"
signal is applied to CTSi
6
Set to "0" by an interrupt request acknowledgement or by
Data is transferred from the UiTB register to the UARTi transmit register
D
7
D
0
D
1
D
0
Read by the UiRB register
D
2
D
An "L" signal is applied when
the UiRB register is read
T
NOTES:
1
D
C
3
=T
1. The CNT3 to CNT0 bits in the TCSPR register select no division (
D
fj : Count source frequency set in the UiBRG register (f
m : Setting value of the UiBRG register
i = 0 to 4
2
n=0) or divide-by-2n (n=1 to 15).
D
CLK
Meet the following conditions while an "H" signal is applied to
the CLKi pin before receiving data:
4
D
program
• Set the TE bit in the UiC
• Set the RE bit in the UiC
• Write dummy data to the UiTB register
3
D
=2(m+1)/fj
5
D
17. Serial I/O (Clock Synchronous Serial I/O)
4
D
6
D
5
D
7
D
6
Pulse stops because the TE bit is set to "0"
D
7
D
0
D
0
D
1
1
1
D
register to "1" (transmit enable)
register to "1" (receive enable)
1
D
2
D
2
D
3
D
3
D
4
D
4
D
5
D
5
D
6
D
6
D
7
1
, f
8
, f
2n (1)
)