M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 434

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Figure 25.10 Block Erase Command
0
C
1
9
0 .
B
8 /
0
1
25.3.5.5 Block Erase Command
4
0
The block erase command erases each block.
Auto erase operation (erase and verify) will start in the specified block by writing command code
"xx20
bus cycle.
The FMR00 bit in the FMR0 register indicates whether or not an auto erase operation has been
completed. The FMR00 bit is set to "0" (busy) during auto erase and to "1" (ready) when the auto
erase operation is completed.
After the completion of an auto erase operation, the FMR07 bit in the FMR0 register indicates whether
or not the auto erase operation has been completed as expected. (Refer to 25.3.8 Full Status
Check.)
Figure 25.10 shows a flow chart of the block erase command programming.
The lock bit can protect each block from being programmed inadvertently. (Refer to 25.3.6 Data
Protect Function.)
In EW mode 1, do not execute this command on the block where the rewrite control program is allocated.
In EW mode 0, the microcomputer enters read status register mode as soon as an auto erase opera-
tion starts. The SRD register can be read. The SR7 bit in the SRD register is set to "0" at the same
time an auto erase operation starts. It is set to "1" when an auto erase operation is completed. The
microcomputer remains in read status register mode until the read array command or read lock bit
status command is written.
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G
6
u
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0 -
. l
u
0
1
, 7
0
p
16
1
(
2
" in the first bus cycle and "xxD0
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0
0
3
5
2
C
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Page 411
, 4
M
NOTES:
3
1. Write the command code and data to even addresses.
2
C
f o
8 /
4
4
) T
9
5
Write the command code "xx20
Write "xxD0
Block erase operation
16
order block address
Full status check
" to the highest-order even address of a block in the second
is completed
FMR00=1?
16
Start
" to the highest-
YES
NO
16
"
25. Flash Memory Version