M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 22

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30845FJGP#U3M30845FJGP
Manufacturer:
TI
Quantity:
18 562
Company:
Part Number:
M30845FJGP#U3
Manufacturer:
MIT
Quantity:
2 367
Company:
Part Number:
M30845FJGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30845FJGP#U3M30845FJGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
M30845FJGP#U3M30845FJGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M
R
2.1 General Registers
e
3
. v
2
C
2.1.1 Data Registers (R0, R1, R2 and R3)
2.1.2 Address Registers (A0 and A1)
2.1.3 Static Base Register (SB)
2.1.4 Frame Base Register (FB)
2.1.5 Program Counter (PC)
2.1.6 Interrupt Table Register (INTB)
2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
2.1.8 Flag Register (FLG)
1
2 .
8 /
R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be
split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers.
R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and
R3.
A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arith-
metic and logic operations.
SB is a 24-bit register for SB-relative addressing.
FB is a 24-bit register for FB-relative addressing.
PC, 24 bits wide, indicates the address of an instruction to be executed.
INTB is a 24-bit register indicating the starting address of an relocatable interrupt vector table.
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP
and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even
addresses to execute an interrupt sequence efficiently.
FLG is a 16-bit register indicating a CPU state.
1
4
2.1.8.1 Carry Flag (C)
2.1.8.2 Debug Flag (D)
2.1.8.3 Zero Flag (Z)
2.1.8.4 Sign Flag (S)
The C flag indicates whether carry or borrow has occurred after executing an instruction.
The D flag is for debug only. Set to "0".
The Z flag is set to "1" when the value of zero is obtained from an arithmetic operation; otherwise "0".
The S flag is set to "1" when a negative value is obtained from an arithmetic operation; otherwise "0".
G
J
u
o r
. l
u
0
p
, 8
(
2
M
0
3
0
5
2
C
8 /
Page 20
, 4
M
3
2
C
f o
8 /
8
4
5
) T
2. Central Processing Unit (CPU)