D6417729RHF200BV Renesas Electronics America, D6417729RHF200BV Datasheet - Page 179
D6417729RHF200BV
Manufacturer Part Number
D6417729RHF200BV
Description
IC SUPER H MPU ROMLESS 208QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417729RF133BV.pdf
(857 pages)
Specifications of D6417729RHF200BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
D6417729RHF200BV
Manufacturer:
EVERLIGHT
Quantity:
1 000
Company:
Part Number:
D6417729RHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
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4.4
4.4.1
The reset sequence is used to power up or restart the SH7729R from the initialization state. The
RESETP and RESETM signals are sampled every clock cycle, and in the case of a power-on reset,
all processing being executed (excluding the RTC) is suspended, all unfinished events are
canceled, and reset processing is executed immediately. In the case of a manual reset, however,
reset processing is executed after completion of any memory access being executed. The reset
sequence consists of the following operations:
1. The MD bit in SR is set to 1 to place the SH7729R in privileged mode.
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except the NMI interrupt
3. The RB bit in SR is set to 1.
4. An encoded value of H'000 in a power-on reset or H'020 in a manual reset is written to bits 11–
5. Instruction execution jumps to the user-written exception handler at address H'A0000000.
4.4.2
An interrupt handling request is accepted on completion of the current instruction. The interrupt
acceptance sequence consists of the following operations:
1. The contents of PC and SR are saved to SPC and SSR, respectively.
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except the NMI interrupt
3. The MD bit in SR is set to 1 to place the SH7729R in privileged mode.
4. The RB bit in SR is set to 1.
5. An encoded value identifying the exception event is written to bits 11–0 of the INTEVT and
6. Instruction execution jumps to the vector location designated by the sum of the value of the
when the BLMSK bit is 1).
0 of the EXPEVT register to identify the exception event.
when the BLMSK bit is 1).
INTEVT2 registers.
contents of the vector base register (VBR) and H'00000600 to invoke the exception handler.
Exception Handling Operation
Reset
Interrupts
Rev. 5.0, 09/03, page 131 of 806
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