D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 453
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 453 of 1418
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10.6.8
The byte control SRAM interface is a memory interface that outputs a byte select strobe (WEn) in
both read and write bus cycles. This interface has 16-bit data pins and can be connected to SRAM
having upper byte select strobe and lower byte select strobe functions such as UB and LB.
Areas 1 and 4 can be specified as a byte control SRAM interface. However, when these areas are
set to MPX mode, MPX mode has priority.
The write timing for the byte control SRAM interface is identical to that of the normal SRAM
interface.
In read operations, on the other hand, the WEn pin timing is different. In a read access, only the
WE signal for the byte being read is asserted. Assertion is synchronized with the falling edge of
the CKIO clock in the same way as the WE signal, while negation is synchronized with the rising
edge of the CKIO clock in the same way as the RD signal.
Figure 10.55 MPX Interface Timing 12 (Burst Write Cycle, AnW = 1, One External Wait
Byte Control SRAM Interface
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
CKIO
RD/FRAME
D31−D0
CSn
RD/WR
RDY
BS
DACKn
(DA)
Inserted, 32-Bit Bus Width, 64-Bit Data Transfer)
Tm1
A
Tmd1w
Tmd1w
D0
Tmd1
Rev. 2.00 Feb. 12, 2010 Page 369 of 1330
Tmd2
D1
REJ09B0554-0200
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