D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 844
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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21.3.7
HcHCCA stores physical addresses of the host controller communication area (HCCA). HCD
determines the alignment restrictions by writing 1 to all bits in HcHCCA and by reading the
contents of HcHCCA. Alignment is evaluated by checking the number of 0s in the low-order bits.
The minimum alignment is 256 bytes. Consequently, bits 0 to 7 must always return 0 when they
are read. This area is used to retain the control structures and interrupt table that are accessed by
HC and HCD.
Initial value:
Initial value:
Bits
31 to 8
7 to 0
21.3.8
HcPeriodCurrentED stores the address of the isochronous ED or interrupt ED to be processed in
the current frame.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 760 of 1330
REJ09B0554-0200
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Host Controller Communication Area Pointer Register (HcHCCA)
Period Current ED Pointer Register (HcPeriodCurrentED)
Bit Name
HCCA
⎯
R/W
R/W
31
15
31
15
R
R
0
0
0
0
R/W
R/W
30
14
30
14
R
R
0
0
0
0
R/W
R/W
29
13
29
13
R
R
0
0
0
0
Initial Value
All 0
All 0
R/W
R/W
28
12
28
12
R
R
0
0
0
0
HCCA
R/W
R/W
27
11
27
11
R
R
0
0
0
0
R/W
R/W
R/W
R/W
R
26
10
26
10
R
R
0
0
0
0
PCED
R/W
R/W
25
25
R
R
0
9
0
0
9
0
Description
Host Controller Communication Area Address
These bits store the base address of HCCA.
Reserved
These bits are always read as 0. Always write 0 to
this bit.
R/W
R/W
24
24
R
R
0
8
0
0
8
0
HCCA
PCED
R/W
23
23
0
7
0
R
0
R
7
0
R
-
R/W
22
22
0
R
R
0
R
0
6
0
6
-
R/W
21
21
0
5
0
R
0
R
5
0
R
-
R/W
20
20
0
4
0
R
0
R
4
0
R
-
R/W
19
19
0
3
0
R
0
R
3
0
R
-
-
R/W
18
18
0
2
-
0
R
0
R
2
-
0
R
R/W
17
17
0
1
0
R
0
R
1
0
R
-
-
R/W
16
16
0
0
0
R
0
R
0
0
R
-
-
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