MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1049

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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24.14.2.4 RCPU Development Access Flow Diagram
Figure 24-83
signals.
Freescale Semiconductor
DEBUG MODE NOT ENALBED
*(exit loop via READI reset (*A*)
or system reset (*B*))
(synch.self-clk mode)
Device sends DSDO Message
Tool sends DSDI Message
*A*
*B*
has flow diagram describing how the RCPU development access can be achieved via READI
(@ subsequent READI reset)
DSDI=1
(@ subsequent RCPU reset)
(DME=0)
Figure 24-83. RCPU Development Access Flow Diagram
DSCK=0 within 8 clocks of SRESET
(Debug Mode not enabled) No
negation to NOT enter debug mode
DSDI=1 (sync. self-clk mode)
MPC561/MPC563 Reference Manual, Rev. 1.2
(No Debug out-of-reset) No
Tools Negates HRESET 16 clocks after receiving Device Ready
Tool sends Download Request Message and configures
*(exit loop via
READI reset
(*A*) or via
system reset
(*B*))
READI module (assign DPA, DME & DOR, etc.)
(DPA, DME, DOR, etc. bits locked)
Tool Asserts and Negates RSTI
DEBUG MODE ENABLED
Device sends DID message
No
No
Entry?
BDM
Exit?
BDM
Device sends DSDO Message
Tool sends DSDI Message
Tool Asserts HRESET
DME=1
DOR=1
(DME=1)
Device sends Debug Mode Status
?
?
Yes
Yes (Debug Mode enabled)
Yes
DSCK=1 until 16 clocks after SRESET
“BDM entry” (status bit = 1)
Device sends Debug Mode
“BDM exit” (status bit = 0)
negation to enter debug mode
DSDI=1 (sync. self-clk mode)
Status Message
Yes (Debug out-of-reset)
Message
READI Module
24-81

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