MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1090

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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MPC562/MPC564 Compression Features
A.2.2
No address arithmetic is allowed for instruction space because the address map changes during
compression and no software tool can identify address arithmetic structures in the code. Address
arithmetic for data tables is permitted since data space is not compressed. Only instruction space is
compressed.
A.2.3
The code compression algorithm is based on creating optimal vocabularies of frequently appearing RCPU
RISC instructions or instruction halves and replacing these instructions with pointers to the vocabularies.
The system contains several sets of vocabularies for different groups of instructions. These groups are
referred to as classes.
Every instruction belongs to exactly one class. Compression of the instructions in a class may be in one of
the following modes. Refer to
A-2
1. Compression of the whole instruction into one vocabulary pointer
2. Compression of each half of the instruction into a different vocabulary
No changes in the CPU architecture
A compressor tool performs compression off-line in software using instruction class-based
algorithms optimized for the MPC56x instruction set
Decompression is done at run-time by special hardware
Optimized for cache-less systems:
— Highly effective in system solutions for a low-cache hit ratio environment and for systems with
— Deterministic program execution
— No performance penalty during sequential program flow execution
— Minimal performance penalty due to change of program flow execution
Switches between compressed and non-compressed user application sections is possible. (A
compressed subroutine can call a non-compressed one and be called from non-compressed portions
of the user application)
Adaptive vocabularies, generated for a particular application
Compressed address space is up to 1 Gbyte
Branch displacement from its target:
— Conditional branch displacement is up to 4 Kbytes
— Unconditional branch displacement is up to 4 Mbytes
fast embedded program memory
Model Limitations
Instruction Class-Based Compression Algorithm
Branch displacement is hardware limited. The compiler can enlarge the
branch scope by creating branch chains.
Figure
MPC561/MPC563 Reference Manual, Rev. 1.2
A-1.
NOTE
Freescale Semiconductor

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