MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1094

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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MPC562/MPC564 Compression Features
When a change of flow occurs, the RCPU issues the new address in compression format. The address
extractor unit of the BBC extracts the base address to instruction memory. When the compressed memory
word is brought to the BBC from the memory, the ICDU uses the IP field of the RCPU-issued address to
decompress the instruction. The BBC provides compressed addresses of the decompressed and next
instructions to the RCPU together with the decompressed instruction.
Shortened word pointer fields of direct branches in compressed mode imply some limitations on compilers
that implement the PowerPC ISA architecture. They should generate binaries, with limited direct branch
displacements to make the compression possible.
If a conditional branch target, generated by a compiler, must be farther than the compression mode
limitation of 4 Kbytes, the compiler may generate a sequence of a conditional branch with opposite
condition to skip the following unconditional branch to the original target.
If the unconditional branch range is still not big enough, the compiler can use branch chains or indirect
branches.
A.2.5
The indirect branch destination address is copied without any change from one of the following RCPU
registers:
See the RCPU User’s Manual for more details.
These registers should contain (or be loaded by) the 32-bit compressed address of existing compressed
instructions to be used for correct branching.
The LR register is automatically updated by the correct value of the “next” instruction compressed address
during subroutine calls by using the ‘L’ - form of branch instructions (like bl or bcl).
The SRR0 register is updated by the correct return compressed address when exceptions are taken by the
RCPU, thus the rfi instruction obtains the correct return address from an exception handler.
A.2.6
Upon an exception, the RCPU core issues a regular 0xFFF00X00 or 0x00000X00 exception vector as
specified in the PowerPC ISA architecture. The compressed exception routines (or branches to them)
should start (reside) at the same location in memory as noncompressed ones. The BBC ICDU passes the
vectors unchanged to the MCU internal bus and provides corresponding compressed address to the RCPU
together with the first exception handler instruction opcode.
This scheme allows use of the BBC exception relocation feature regardless of the MCU operational mode.
The RESET routine vector is relocated differently in decompression on and in decompression off modes.
This feature may be used by a software code compression tool to guarantee that a vocabulary table
initialization routine is always executed before application code is running.
A-6
LR
CTR
SRR0
Compressed Address Generation—Indirect Branches
Compressed Address Generation—Exceptions
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor

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