MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1106

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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MPC562/MPC564 Compression Features
A.4
The DCCR fields are programmed to achieve maximum flexibility in the vocabulary tables placement into
the two DECRAM banks under constraints, implied by hardware, which are:
A-18
1
Serialize
Control
MPC562/MPC564 only.
29:31
Bits
(SER)
28
A bypass field must always be in the second field of the compressed instruction
0
0
0
0
1
1
1
1
Decompressor Class Configuration Registers (DCCR0-15)
Mnemonic
ISCT_SER
Instruction
(ISCTL)
IFM
Fetch
00
01
10
11
00
01
10
11
Ignore first match, only for I-bus
breakpoints
RCPU serialize control and
Instruction fetch show cycle
RCPU is fully serialized and show cycles will be performed for all fetched instructions (reset
value)
RCPU is fully serialized and show cycles will be performed for all changes in the program flow
RCPU is fully serialized and show cycles will be performed for all indirect changes in the
program flow
RCPU is fully serialized and no show cycles will be performed for fetched instructions
Illegal. This mode should not be selected.
RCPU is not serialized (normal mode) and show cycles will be performed for all changes in
the program flow
RCPU is not serialized (normal mode) and show cycles will be performed for all indirect
changes in the program flow
RCPU is not serialized (normal mode) and no show cycles will be performed for fetched
instructions
Table A-1. ICTRL Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Table A-2. ISCT_SER Bit Descriptions
0 = Do not ignore first match,
used for “go to x” (reset
value)
1 = Ignore first match (used
for “continue”)
These bits control
serialization and instruction
fetch show cycles. See
Table A-2
definitions.
NOTE: Changing the
instruction show cycle
programming starts to take
effect only from the second
instruction after the actual
mtspr to ICTRL.
Non-compressed mode
Functions Selected
for the bit
Function
0 = Do not ignore first match,
used for “go to x” (reset
value)
1 = Ignore first match (used
for “continue”)
These bits control
serialization and instruction
fetch show cycles. See
Table A-2
definitions.
NOTE: Changing the
instruction show cycle
programming starts to take
effect only from the second
instruction after the actual
mtspr to ICTRL.
Compressed Mode
Freescale Semiconductor
for the bit
1

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