MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 205

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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detected and data storage interrupt is never generated by the hardware. In the RCPU, the instruction can
be partially executed only in the case of the load/store instructions that cause multiple accesses to the
memory subsystem. These instructions are:
In the last case, the store instruction can be partially completed if one of the accesses (except the first one)
causes the data storage protection error. The implementation-specific data storage protection interrupt is
taken in this case. For the update forms, the update register (rA) is not altered.
3.15.6
Descriptions of the timebase and decrementer registers can be found in
and
3.15.7
Any other OEA optional facilities and instructions (except those that are discussed here) are not
implemented by the RCPU hardware. Attempting to execute any of these instructions causes an
implementation dependent software emulation interrupt to be taken.
Freescale Semiconductor
Protection,” and in
Multiple/string instructions
Unaligned load/store instructions
Timer Facilities
Optional Facilities and Instructions
Chapter 8, “Clocks and Power
MPC561/MPC563 Reference Manual, Rev. 1.2
Control.”
Chapter 6, “System Configuration
Central Processing Unit
3-61

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