MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 318

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Clocks and Power Control
The default value of the LME bit is determined by MODCK[1:3] during assertion of the PORESET line.
The configuration modes are shown in
8.7
The LPM and other bits in the PLPRCR are encoded to provide one normal operating mode and four
low-power modes. In normal and doze modes the system can be in high state with frequency defined by
the DFNH bits, or in the low state with frequency defined by the DFNL bits. The normal-high operating
mode is the state out of reset. This is also the state of the bits after the low-power mode exit signal arrives.
There are four low-power modes:
8.7.1
Low-power modes are enabled by setting the MSR[POW] and clearing the SCCR[LPML]. Once enabled,
a low-power mode is entered by setting the LPM bits to the appropriate value. This can be done only in
one of the normal modes. The user cannot change the PLPRCR[LPM or CSRC] when the MCU is in doze
mode.
8-16
•
•
•
•
Doze mode
Sleep mode
Deep-sleep mode
Power-down mode
Low-Power Modes
1
2
STATE
Entering a Low-Power Mode
At least one of the two bits, LOCSS or BUCS, must be asserted (one) in this state.
X = don’t care.
3
1
2
4
5
6
1
The switching from state three to state four is accomplished by clearing the
STBUC and LOCSS bits. If the switching is done when the PLL is not
locked, the system clock will not oscillate until lock condition is met.
Higher than desired currents during low-power mode can be avoided by
executing a mullw instruction before entering the low-power mode, i.e.,
anytime after reset and prior to entering the low-power mode.
PORESET
0
1
1
1
1
1
HRESET
MPC561/MPC563 Reference Manual, Rev. 1.2
0
0
1
0
1
0
Table 8-3. Status of Clock Source
Table
LME
0/1
0/1
1
1
1
1
8-1.
NOTE
(status)
LOCS
0/1
0/1
x
0
0
0
2
LOCSS
(sticky)
0/1
x
x
0
0
1
2
2
STBUC
0/1
0/1
0
0
0
0
BUCS
1
1
1
0
0
1
Freescale Semiconductor
Oscillator
Oscillator
Source
BUCLK
BUCLK
BUCLK
BUCLK
Clock
Chip