MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 324

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Clocks and Power Control
8.8.2
The MPC561/MPC563 provides a wide range of possibilities for power supply connections.
illustrates the different power supply sources for each of the basic units on the chip.
8.8.2.1
This supplies the final output stage of the 2.6-V pad output drivers.
8.8.2.2
This supplies all pad logic and pre-driver circuitry, except for the final output stage of the 2.6-V pad output
drivers.
8.8.2.3
VDD powers the internal logic of the MPC561/MPC563, nominally 2.6V.
8.8.2.4
The charge pump and the VCO of the SPLL are fed by a separate 2.6-V power supply (VDDSYN) in order
to improve noise immunity and achieve a high stability in its output frequency. VSSSYN provides an
isolated ground reference for the PLL.
8.8.2.5
The oscillator, time base counter, decrementer, periodic interrupt timer and the real-time clock are fed by
the KAPWR rail. This allows the external power supply unit to disconnect all other sub-units of the MCU
in low-power deep-sleep mode. The TEXP pin (fed by the same rail) can be used by the external power
supply unit to switch between sources. The IRQ[6:7]/MODCK[2:3], IRQ5/MODCK1, XTAL, EXTAL,
EXTCLK, PORESET
Circuits, including pull-up resisters, driving these inputs should be powered by KAPWR.
8.8.2.6
VDDA supplies power to the analog subsystems of the QADC64E_A and QADC64E_B modules; it is
nominally 5.0 V. VSSA is the ground reference for the analog subsystems.
8.8.2.7
VFLASH supplies the UC3F normal operating voltage. It is nominally 5.0 V. The MPC561 has no
VFLASH signal.
8.8.2.8
VDDF provides internal core voltage to the UC3F Flash module; it should be a nominal 2.6V. VSSF
provides an isolated ground for the UC3F Flash module. The MPC561 has no VDDF or VSSF signal.
8-22
Chip Power Structure
NVDDL
QVDDL
VDD
VDDSYN, VSSSYN
KAPWR
VDDA, VSSA
VFLASH
VDDF, VSSF
,
HRESET, SRESET, and RSTCONF/TEXP input pins are powered by KAPWR.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
Figure 8-11