MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 327

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

The MPC561/MPC563 asserts the TEXP signal, if enabled, when the RTC or TB time value matches the
value programmed in the associated alarm register or when the PIT or DEC value reaches zero. The TEXP
signal is negated when the TEXPS status bit is written to one.
The KAPWR power supply feeds the main crystal oscillator (OSCM). The condition for the main crystal
oscillator stability is that the power supply value changes slowly. The maximum slope must be less than 5
mV per oscillation cycle (
8.8.3.2
The USIU timer, clocks, reset, power, decrementer, and time base registers are powered by the KAPWR
supply. When the main power supply is disconnected after power-down mode is entered, the value stored
in any of these registers is preserved. If power-down mode is not entered before power disconnect, there
is a chance of data loss in these registers. To minimize the possibility of data loss, the MPC561/MPC563
includes a key mechanism that ensures data retention as long as a register is locked. While a register is
locked, writes to this register are ignored.
Each of the registers in the KAPWR region have a key that can be in one of two states: open or locked. At
power-on reset the following keys are locked by default: RTC, RTSEC, RTCAL, and RTCSC. All other
registers are unlocked. Each key has an address associated with it in the internal map.
Freescale Semiconductor
MPC561/MPC563
Keep-Alive Power Registers Lock Mechanism
IRAMSTBY
TEXP
KAPWR
VDDSYN
VDD
τ
> 200-300/freq
Figure 8-12. External Power Supply Scheme
Switch
Logic
MPC561/MPC563 Reference Manual, Rev. 1.2
oscm
O
O
O
O
SW1
).
SW2
Backup
Supply
Power
2.6-V
Main Power
Supply
2.6 V
Power Supply
IRAMSTBY
Clocks and Power Control
8-25