MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 336

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Clocks and Power Control
8-34
PORESET
PORESET
HRESET
HRESET
Bits
0:11
12
13
14
15
Field
Field SPLSS TEXPS TEXP_INV TMIST — CSRC LPM CSR LOLRE —
Addr
MSB
16
U
0
0
LOCSS
Name
LOCS
SPLS
MF
Figure 8-17. PLL, Low-Power, and Reset-Control Register (PLPRCR)
17
1
1
1
Multiplication factor bits. The output of the VCO is divided to generate the feedback signal to
the phase comparator. The MF bits control the value of the divider in the SPLL feedback loop.
The phase comparator determines the phase shift between the feedback signal and the
reference clock. This difference results in either an increase or decrease in the VCO output
frequency.
The MF bits can be read and written at any time. However, this field can be write-protected
by setting the MF and pre-divider lock (MFPDL) bit in the SCCR. Changing the MF bits
causes the SPLL to lose lock. Also, the MF field should not be modified when entering or
exiting from low power mode (LPM change), or when back-up clock is active.
The normal reset value for the DFNH bits is zero (divide by 1). When the PLL is operating in
one-to-one mode, the multiplication factor is set to x1 (MF = 0).
Reserved
Loss of clock status. When the oscillator or external clock source is not at the minimum
frequency, the loss-of-clock circuit asserts the LOCS bit. This bit is cleared when the
oscillator or external clock source is functioning normally. This bit is reset only on power-on
reset. Writes to this bit have no effect.
0 No loss of oscillator is currently detected
1 Loss of oscillator is currently detected
Loss of clock sticky. If, after negation of PORESET, the loss-of-clock circuit detects that the
oscillator or external clock source is not at a minimum frequency, the LOCSS bit is set.
LOCSS remains set until software clears it by writing a one to it. A write of zero has no effect
on this bit. The reset value is determined during hard reset. The STBUC bit will be set
provided the PLL lock condition is not met when HRESET is asserted, and cleared if the PLL
is locked when HRESET is asserted.
0 No loss of oscillator has been detected
1 Loss of oscillator has been detected
System PLL lock status bit
0 SPLL is currently not locked
1 SPLL is currently locked
0000_0000_0000 or 0000_0000_1000
18
U
2
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 8-11. PLPRCR Bit Descriptions
19
0
3
20
U
4
MF
21
5
000
0x2F C284
Unaffected
22
6
00_0000_0000_0000
23
7
Description
24
Unaffected
8
25
9
10
26
11
27
— LOCS LOCSS SPLS
12
28
Freescale Semiconductor
Unaffected
13
29
DIVF
0000
14
30
LSB
15
31

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