MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 41

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Figure
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Freescale Semiconductor
MPC561/MPC563 Block Diagram ........................................................................................... 1-3
Recommended Connection Diagram for IRAMSTBY........................................................... 1-11
MPC561/MPC563 Memory Map ........................................................................................... 1-12
MPC561/MPC563 Internal Memory Map .............................................................................. 1-14
MPC561/MPC563 Signal Groupings ....................................................................................... 2-2
Pads Module Configuration Register (PDMCR) .................................................................... 2-22
Pads Module Configuration Register 2 (PDMCR2) ............................................................... 2-23
Debug Mode Selection (JTAG) .............................................................................................. 2-30
Debug Mode Selection (BDM)............................................................................................... 2-30
Debug Mode Selection (Nexus).............................................................................................. 2-31
RCPU Block Diagram .............................................................................................................. 3-2
Sequencer Data Path ................................................................................................................. 3-4
RCPU Programming Model ..................................................................................................... 3-8
General-Purpose Registers (GPRs)......................................................................................... 3-12
Floating-Point Registers (FPRs) ............................................................................................. 3-13
Floating-Point Status and Control Register (FPSCR)............................................................. 3-14
Condition Register (CR) ......................................................................................................... 3-16
Integer Exception Register (XER) .......................................................................................... 3-18
Link Register (LR).................................................................................................................. 3-19
Count Register (CTR) ............................................................................................................. 3-19
Machine State Register (MSR) ............................................................................................... 3-20
DAE/Source Instruction Service Register (DSISR) ............................................................... 3-22
Data Address Register (DAR) ................................................................................................ 3-23
Machine Status Save/Restore Register 0 (SRR0) ................................................................... 3-23
Machine Status Save/Restore Register 1 (SRR1) ................................................................... 3-24
SPRG0–SPRG3 — General Special-Purpose Registers 0–3 .................................................. 3-24
Processor Version Register (PVR) ......................................................................................... 3-25
Floating-Point Exception Cause Register (FPECR) ............................................................... 3-26
Basic Instruction Pipeline ....................................................................................................... 3-38
BBC Module Block Diagram ................................................................................................... 4-2
Exception Table Entries Mapping ............................................................................................ 4-8
External Interrupt Vectors Splitting........................................................................................ 4-12
DECRAM Interfaces Block Diagram ..................................................................................... 4-13
BTB Block Diagram ............................................................................................................... 4-16
MPC561/MPC563 Memory Map ........................................................................................... 4-17
BBC Module Configuration Register (BBCMCR)................................................................. 4-19
Region Base Address Register (MI_RBA[0:3]) ..................................................................... 4-21
Region Attribute Register (MI_RA0[0:3]) ............................................................................. 4-22
Global Region Attribute Register (MI_GRA) ........................................................................ 4-23
MPC561/MPC563 Reference Manual, Rev. 1.2
Figures
Title
Number
Page
xli

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