MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 448

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

L-Bus to U-Bus Interface (L2U)
Table 11-4
11.8
The L2U control registers control the L2U bus interface and the DMPU. They are accessible via the mtspr
and mfspr instructions. They are also accessible by an external master when EMCR[CONT] bit is cleared.
L2U control registers are accessible from both the L-bus side and the U-bus side in one clock cycle. As
with all SPRs, L2U registers are accessible in supervisor mode only.
Any unimplemented bits in L2U registers return 0’s on a read, and the writes to those register bits are
ignored.
Table 11-5
access L2U registers during a peripheral mode access.
11-12
.
•
L2U_RBA0
L2U_RBA1
L2U_RBA2
L2U_RBA3
L2U_MCR
L2U_RA0
L2U_RA1
Name
The L2U does not provide show cycle for any L-bus addresses that fall in the L-bus CALRAM
address space if the CALRAM protection [SP] bit is set in the L2U_MCR.
L2U Programming Model
1
2
3
4
5
shows L2U registers along with their SPR numbers and hexadecimal addresses that are used to
summarizes the L2U show cycle support.
Case
L-bus slave includes all address in the L-bus address space.
X indicates don’t care conditions.
There will be a 1-clock turnaround because the L-bus retry information is not available in time to
negate the L-bus arbitration.
L2U indicates L2U registers.
U-bus/E-bus refers to all destinations through the L2U interface.
1
2
3
4
5
SPR #
568
792
793
794
795
824
825
U-bus/E-bus
L-bus Slave
Destination
L-bus slave
L-bus slave
L2U
SPR[5:9]
10001
11000
11000
11000
11000
11001
11001
4
1
1
1
5
Table 11-4. L2U Show Cycle Support Chart
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 11-5. L2U (PPC) Register Decode
SPR[0:4]
11000
11000
11001
11010
11011
11000
11001
LB AACK
Yes
Yes
No
X
X
External Master
0x0000_3110
0x0000_3180
0x0000_3380
0x0000_3580
0x0000_3780
0x0000_3190
0x0000_3390
Address for
Access
LB ABORT
Yes
No
X
X
X
2
1
Access
SUPR
SUPR
SUPR
SUPR
SUPR
SUPR
SUPR
[Cycle will be retried one clock later]
[L-bus will be released next clock]
Not show cycled
Not show cycled
Not show cycled
Not show cycled
L2U Module Configuration Register
Region Base Address Register 0
Region Base Address Register 1
Region Base Address Register 2
Region Base Address Register 3
Show cycled
Comments
Region Attribute Register 0
Region Attribute Register 1
Description
Freescale Semiconductor
3