MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 465

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Chapter 13
QADC64E Legacy Mode Operation
The two queued analog-to-digital converter (QADC) modules on MPC561/MPC563 devices are 10-bit,
unipolar, successive approximation converters. The modules can be configured to operate in one of two
modes, legacy mode (MPC555 compatible) and enhanced mode. This chapter describes how the modules
operate in legacy mode, which is the default mode of operation. Refer to
Enhanced Mode
For this revision of the QADC, the name QADC64E implies the enhanced version of the QADC module,
not just enhanced mode of operation. For simplicity, the names QADC and QADC64E may be used
interchangeably throughout this document.
13.1
Figure 13-1
Freescale Semiconductor
EXTERNAL
Triggers
QADC64E Block Diagram
displays the major components of the QADC64E modules on the MPC561/MPC563.
CONTROL
Operation,” for information regarding the QADC64E functionality in enhanced mode.
DIGITAL
IMB3
MUX Address
EXTERNAL
BUS INTERFACE UNIT
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 13-1. QADC64E Block Diagram
(BIU)
Command Words (CCW), 64 Entries
Queues OF 10-BIT Conversion
ANALOG Input Multiplexor and
DIGITAL Signal Functions
Up to 16 ANALOG
Input Signals
10-bit ANALOG to DIGITAL CONVERTER
REFERENCE
10-bit RESULT Table,
Chapter 14, “QADC64E
Inputs
RESULT Alignment
64 Entries
10-bit to 16-bit
ANALOG POWER
Inputs
13-1