MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 471

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Table 13-4
multiplexer chips using one QADC module.
13.3
The QADC64E has three global registers for configuring module operation:
The global registers are always defined to be in supervisor-only data space. Refer to
QADC64E_A address map and
“Supervisor/Unrestricted Address
The remaining five registers in the control register block control the operation of the queuing mechanism,
and provide a means of monitoring the operation of the QADC64E.
Freescale Semiconductor
I
Module configuration register
(QADMCR)”)
Interrupt register
Test register (QADCTEST) for factory tests.
Control register 0 (QACR0) contains hardware configuration information
“Control Register 0
Control register 1 (QACR1) is associated with queue 1
(QACR1)”)
Control register 2 (QACR2) is associated with queue 2
(QACR2)”)
Programming the QADC64E Registers
shows the total number of analog input channels supported with zero to four external
No External
If either QADC64E_A or QADC64E_B is in external multiplexing
(EMUX) mode then the multiplexer address signal channels, AN[52:54]
should not be programmed into queues.
MUX Chips
16
Multiplexed Analog Input
(Section 13.3.2, “QADC64E Interrupt Register
Directly Connected + External Multiplexed = Total Channels
(QACR0)”)
NOTE: QADC64E External MUX Users
ANw (AN[0])
ANx (AN[1])
ANy (AN[2])
ANz (AN[3])
Table 13-3. Multiplexed Analog Input Channels
One External
MUX Chip
Table 13-2
MPC561/MPC563 Reference Manual, Rev. 1.2
Number of Analog Input Channels Available
Space” for access modes of these registers.
20
Table 13-4. Analog Input Channels
(Section 13.3.1, “QADC64E Module Configuration Register
for the QADC64E_B address map. See
Two External
MUX Chips
27
16, 18, 20, 22, 24, 26, 28, 30
17, 19, 21, 23, 25, 27, 29, 31
0, 2, 4, 6, 8, 10, 12, 14
1, 3, 5, 7, 9, 11, 13, 15
Channels
Three External
(Section 13.3.6, “Control Register 1
(Section 13.3.7, “Control Register 2
MUX Chips
34
(QADCINT)”
QADC64E Legacy Mode Operation
Four External
MUX Chips
(Section 13.3.5,
Section 13.3.1.4,
41
Table 13-1
for the
13-7

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