MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 49

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Freescale Semiconductor
Figure
Number
QSPI Status Register (SPSR)................................................................................................ 15-21
QSPI RAM............................................................................................................................ 15-23
CR[0:F] — Command RAM 0x30 51C0, 0x30 51DF.......................................................... 15-24
Flowchart of QSPI Initialization Operation.......................................................................... 15-28
Flowchart of QSPI Master Operation (Part 1) ...................................................................... 15-29
Flowchart of QSPI Master Operation (Part 2) ...................................................................... 15-30
Flowchart of QSPI Master Operation (Part 3) ...................................................................... 15-31
Flowchart of QSPI Slave Operation (Part 1) ........................................................................ 15-32
Flowchart of QSPI Slave Operation (Part 2) ........................................................................ 15-33
SCI Transmitter Block Diagram ........................................................................................... 15-43
SCI Receiver Block Diagram ............................................................................................... 15-44
SCCxR0 — SCI Control Register 0 ..................................................................................... 15-46
SCI Control Register 1 (SCCxR1)........................................................................................ 15-47
SCIx Status Register (SCxSR).............................................................................................. 15-49
SCI Data Register (SCxDR) ................................................................................................. 15-51
Start Search Example............................................................................................................ 15-57
QSCI1 Control Register (QSCI1CR).................................................................................... 15-60
QSCI1 Status Register (QSCI1SR)....................................................................................... 15-61
Queue Transmitter Block Enhancements ............................................................................. 15-63
Queue Transmit Flow ........................................................................................................... 15-66
Queue Transmit Software Flow ............................................................................................ 15-66
Queue Transmit Example for 17 Data Bytes ........................................................................ 15-67
Queue Transmit Example for 25 Data Frames ..................................................................... 15-69
Queue Receiver Block Enhancements .................................................................................. 15-70
Queue Receive Flow ............................................................................................................. 15-73
Queue Receive Software Flow ............................................................................................. 15-74
Queue Receive Example for 17 Data Bytes.......................................................................... 15-75
TouCAN Block Diagram ........................................................................................................ 16-1
Typical CAN Network............................................................................................................ 16-3
Extended ID Message Buffer Structure .................................................................................. 16-4
Standard ID Message Buffer Structure ................................................................................... 16-4
Relationship between System Clock and CAN Bit Segments ................................................ 16-9
CAN Controller State Diagram............................................................................................. 16-12
Interrupt Levels on IRQ with ILBS ...................................................................................... 16-21
TouCAN Message Buffer Memory Map .............................................................................. 16-24
TouCAN Module Configuration Register (CANMCR) ....................................................... 16-25
TouCAN Interrupt Configuration Register (CANICR) ........................................................ 16-27
Control Register 0 (CANCTRL0)......................................................................................... 16-27
Control Register 1 (CANCTRL1)......................................................................................... 16-28
Prescaler Divide Register...................................................................................................... 16-29
MPC561/MPC563 Reference Manual, Rev. 1.2
Figures
Title
Number
Page
xlix

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