MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 500

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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QADC64E Legacy Mode Operation
13.4.2
The internal multiplexer selects one of the 16 analog input signals for conversion. The selected input is
connected to the sample buffer amplifier. The multiplexer also includes positive and negative stress
protection circuitry, which prevents deselected channels from affecting the selected channel when current
is injected into the deselected channels. Refer to
current levels.
13.4.3
The sample buffer is used to raise the effective input impedance of the A/D converter, so that external
components (higher bandwidth or higher impedance) are less critical to accuracy. The input voltage is
buffered onto the sample capacitor to reduce crosstalk between channels.
13.4.4
The digital to analog converter (DAC) array consists of binary-weighted capacitors and a resistor-divider
chain. The reference voltages, V
DAC also converts the following three internal channels:
The DAC array serves to provide a mechanism for the successive approximation A/D conversion.
Resolution begins with the most significant bit (MSB) and works down to the least significant bit (LSB).
The switching sequence is controlled by the comparator and successive-approximation register (SAR)
logic.
13-36
V
V
(V
Sample capacitor — The sample capacitor is employed to sample and hold the voltage to be
converted.
RH
RL
RH
— Reference voltage low
Channel Decode and Multiplexer
Sample Buffer Amplifier
Digital-to-Analog Converter (DAC) Array
— Reference voltage high
– V
RL
QCLK
)/2 — Reference voltage
(2, 4, 8, 16)
N cycles:
Sample
Sample
Time
Time
Figure 13-22. Bypass Mode Conversion Timing
RH
MPC561/MPC563 Reference Manual, Rev. 1.2
and V
RL
Successive Approximation Resolution
, are used by the DAC to perform ratiometric conversions. The
Appendix F, “Electrical
Resolution
Sequence
10 cycles
Time
Characteristics,” for specific
Freescale Semiconductor

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