MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 553

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

The bus master indicates the supervisor and user space access with the function code bits (FC[2:0]) on the
IMB3. For privilege violations, refer to
of a bus error cycle termination.
The supervisor-only data space segment contains the QADC64E global registers, which include the
QADCMCR, QADCINT and QADCTEST. The supervisor/unrestricted space designation for the CCW
table, the result word table and the remaining QADC64E registers is programmable.
14.3.2
QADCINT specifies the priority level of QADC64E interrupt requests. The interrupt level for queue 1 and
queue 2 may be different. The interrupt register is read/write accessible in supervisor data space only. The
implemented interrupt register fields can be read and written, reserved bits read zero and writes have no
effect. They are typically written once when the software initializes the QADC64E, and not changed
afterwards.
Freescale Semiconductor
•
•
attempts to write unimplemented data space, the QADC64E causes a bus error condition and no
data is written.
Attempts to read assignable data space in the unrestricted access mode when the space is
programmed as supervisor space causes the bus master to assert a bus error condition and no data
is returned.
Attempts to write assignable data space in the unrestricted access mode when the space is
programmed as supervisor space causes the bus master to assert a bus error condition and the
register is not written.
QADC64E Interrupt Register
1
2
3
4 Access to QADCTEST register will act as a reserved/unimplemented register unless in factory
Mode
S/U = Supervisor/Unrestricted
QADC64E bus error = Caused by QADC64E
Master bus error = Caused by bus master
test mode
S/U
U
U
S
S
1
SUPV Bit
0
1
0
1
Table 14-6. QADC64E Bus Error Response
MPC561/MPC563 Reference Manual, Rev. 1.2
QADC64E bus error
Supervisor-Only
Master bus error
Valid access
Valid access
Register
Chapter 9, “External Bus
3
2
Unrestricted Register
Master bus error
Valid access
Valid access
Valid access
Supervisor/
Interface” to determine the consequence
4
3
QADC64E bus error
QADC64E bus error
QADC64E bus error
Master bus error
QADC64E Enhanced Mode Operation
Unimplemented
Reserved/
Register
3
2
2
2
14-11