MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 554

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

QADC64E Enhanced Mode Operation
The QADC64E conditionally generates interrupts to the bus master via the IMB3 IRQ signals. When the
QADC64E sets a status bit assigned to generate an interrupt, the QADC64E drives the IRQ bus. The value
driven onto IRQ[7:0] represents the interrupt level assigned to the interrupt source. Under the control of
ILBS, each interrupt request level is driven during the time multiplexed bus during one of four different
time slots, with eight levels communicated per time slot. No hardware priority is assigned to interrupts.
Furthermore, if more than one source on a module requests an interrupt at the same level, the system
software must assign a priority to each source requesting at that level.
levels on IRQ with ILBS. Refer to
information.
14.3.3
QADC64E ports A and B are accessed through two 8-bit port data registers, PORTQA and PORTQB.
14-12
SRESET
10:15
Bits
0:4
5:9
Field
Addr
ILBS [1:0]
IMB3 CLOCK
IMB3 IRQ [7:0]
MSB
Port Data Register
0
Name
IRL2
IRL1
—
1
Queue 1 Interrupt Request Level. The IRL1 field establishes the queue 1 interrupt request level.
The 00000 state provides a level 0 interrupt while 11111 provides a level 31 interrupt. All
interrupts are presented on the IMB3. Interrupt level priority software determines which level has
the highest priority request.
Queue 2 Interrupt Request Level. The IRL2 field establishes the queue 2 interrupt request level.
The 00000 state provides a level 0 interrupt while 11111 provides a level 31 interrupt. All
interrupts are presented on the IMB3. Interrupt level priority software determines which level has
the highest priority request.
Reserved.
IRL1
2
Figure 14-5. QADC Interrupt Register (QADCINT)
Figure 14-6. Interrupt Levels on IRQ with ILBS
3
00
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 14-7. QADCINT Bit Descriptions
Chapter 12, “U-Bus to IMB3 Bus Interface
0x30 4804 (QADCINT_A); 0x30 4C04 (QADCINT_B)
4
01
IRQ
7:0
5
10
IRQ
15:8
0000_0000_0000_0000
6
IRL2
23:16
11
IRQ
7
Description
8
31:24
00
IRQ
9
01
IRQ
7:0
Figure 14-6
10
10
11
(UIMB)” for more
displays the interrupt
12
11
Freescale Semiconductor
—
13
14
LSB
15